Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators

Co-exploration of neural architectures and hardware design is promising due to its capability simultaneously optimize network accuracy efficiency. However, state-of-the-art architecture search algorithms for the co-exploration are dedicated conventional von-Neumann computing architecture, whose performance heavily limited by well-known memory wall. In this article, we first bring computing-in-memory which can easily transcend wall, interplay with search, aiming find most efficient high maximized Such a novel combination makes opportunities boost performance, but also brings bunch challenges: The optimization space spans across multiple layers from device type circuit topology architecture; presence variation may drastically degrade performance. To address these challenges, propose cross-layer exploration framework, namely NACIM, jointly explores device, takes into consideration robust architectures, coupled design. Experimental results demonstrate that NACIM 0.45 percent loss in variation, compared 76.44 NAS without variation; addition, achieves an energy efficiency up 16.3 TOPs/W, 3.17x higher than NAS.